1. Field of the Invention
The present invention relates to a semiconductor device provided with a driver circuit for a bit-line load circuit used particularly in a static random access memory (SRAM).
2. Description of the Related Art
FIG. 1 is a circuit diagram of a memory cell and associated circuit in a prior art SRAM. The arrangement of FIG. 1 comprises a memory cell MC, a word line WL for selecting memory cell MC, a pair of bit lines BL and BL provided normal to word line WL for transmitting and receiving data to and from memory cell MC, a bit-line load circuit 30 coupled to bit lines BL and BL, N-channel MOS transistors TS1 and TS2 coupled to bit lines BL and BL adapted for selecting a column, and a pair of data write circuits 31 and 32 coupled to bit lines BL and BL via transistors TS1 and TS2.
Memory cell MC comprises a flip-flop circuit having a pair of N-channel MOS transistors T1 and T2 for data storage and a pair of high-resistance load elements R1 and R2, and a pair of transfer-gate N-channel MOS transistors T3 and T4 coupled between one of input/output nodes of the flip-flop circuit and bit line BL and between the other of input/output nodes of the flip-flop circuit and bit line BL. Bit-line load circuit 30 comprises a pair of N-channel MOS transistors T5 and T6 the drain and gate of each of which are supplied with a supply voltage VDD. Thus T5 and T6 are normally on. Each of data write circuits 31 and 32 is a complementary MOS (CMOS) inverter having a P-channel transistor Tp and an N-channel transistor Tn which are connected in series and whose gates are connected together. Output nodes of the CMOS inverters are coupled to bit lines BL and BL through the MOS transistor TS1 and TS2, respectively.
In the SRAM, to write a logical level "0" into the memory cell, data write circuits 31 and 32 are driven so that outputs din and din thereof may go to a low and a high level, respectively. Further, column select transistors TS1 and TS2 are switched ON by a column decoder output CD, and word line WL is raised to a high level by a word select signal. As a result, bit lines BL and BL go to sufficiently low and high levels, respectively, and the drains of transistors T1 and T2 in memory cell MC go to low and high levels, respectively. In this case, as shown, a direct current Iw flows through a path extending from bit-line load circuit 30, through bit line BL and column select transistor TS1, to data write circuit 31 during a write operation period. The direct current Iw is about 1.about.1.5 mA per column. For example, in an SRAM of 8 bits per word in which 8 columns are selected at the same time, the currents flowing through selected columns will amount to 8.about.12 mA. At this time, a direct current IR will also flow through a nonselected column, IR flows from bit-line load circuit 30, bit line BL and transistors T3 and T1, which approximately equals the direct current IW flowing through a selected column during a read operation. Through all the nonselected columns in the SRAM, currents will flow which approximately equal the currents flowing through the selected columns during a write operation. These form a principal cause of the power dissipation during a write operation in SRAMs.